We move computation closer to data by treating memory arrays as a computational substrate rather than pure storage, reducing the energy and latency of data movement and improving resistance to hardware-level attacks. Our work spans device physics, circuit design, and full accelerator architectures, organized around three research areas.
Conventional computing wastes significant energy and time moving data between memory and processor. We design architectures that embed logic directly into memory arrays — SRAM, DRAM, and emerging non-volatile memories — using both CMOS and beyond-CMOS devices such as ferroelectric FETs (FeFETs), resistive random-access memories (RRAMs), and spin-orbit-torque (SOT) elements. Building on these devices, we design processing-in-memory architectures that let computation and data movement happen concurrently rather than compete for the same resources. We also build ultra-dense, low-leakage content-addressable memory (CAM) arrays from ferroelectric and spintronic devices, including magnetoelectric ternary CAMs for fast, parallel search. To evaluate these designs fairly against conventional approaches, we build device-to-system benchmarking frameworks that project performance and energy across a range of memory technologies, from CMOS to emerging non-volatile devices.
We co-design AI algorithms with the circuits and architectures that run them, favoring formulations that map naturally onto memory-centric hardware rather than adapting hardware to conventional algorithms after the fact. This includes hyperdimensional computing, which replaces the dense matrix multiplications of conventional neural networks with lightweight, high-dimensional vector operations suited to in-memory implementation; attention and content-addressable-memory-based accelerators for few-shot learning, which classify from only a handful of training examples without the retraining cost of standard deep learning; and in-memory embedding-table lookups that accelerate large-scale recommendation systems by keeping computation close to the data. Across these efforts, we favor lightweight, low-power encoding and memory schemes over dense multiply-accumulate arithmetic wherever the workload allows it, and use hardware-aware architecture search to tailor these designs automatically to resource-constrained edge devices.
We design hardware primitives for secure computing and evaluate them against system-level metrics for energy, latency, and reliability. This spans computing-in-memory fabrics that accelerate symmetric-key encryption and decryption directly within random-access and content-addressable memory arrays, and compute-enabled memory architectures for fully homomorphic encryption that have delivered speedups of nearly three orders of magnitude over software baselines for core cryptographic operations. It also includes low-power FeFET crossbar accelerators for Boolean satisfiability (SAT) solving, a core computational step behind logic-locking schemes and their attacks, hardware Trojan detection, and formal verification of secure designs. We further collaborate on two-dimensional transistors with reconfigurable polarity that operate at voltages as low as 0.2V for secure circuit design, and we tie this work to workforce-development efforts that train students in hardware security for cyber-physical energy systems.
Develops memory-centric hardware for energy-efficient, reliable edge AI, using compute-in-memory and near-sensor architectures built on distributed representations (e.g., hyperdimensional computing) instead of dense multiply-accumulate arithmetic, to reduce data movement and improve robustness for always-on sensing applications. USF share: $301,642. Award #2616836.
A collaborative effort among Florida Atlantic University, Florida International University, the University of Central Florida, and the University of South Florida to build workforce pathways in hardware security and cybersecurity through hardware-in-the-loop training. USF share: $385K over 4 years.
Fabrication and assessment of a cryptographic accelerator built on in-memory computing, improving throughput, energy consumption, and latency. Collaborative subaward with the University of Notre Dame, with industry partners Analog Devices (ADI) and RTX. USF share: approximately $165K.
